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Features
* Protocol
- UART used as Physical Layer - Based on the Intel Hex-type records - Autobaud * In-System Programming - Read/Write Flash and EEPROM Memories - Read Device ID - Full-chip Erase - Read/Write Configuration Bytes - Security Setting From ISP Command - Remote Application Start Command * In-Application Programming/Self Programming - Read/Write Flash and EEPROM Memories - Read Device ID - Block Erase - Read/write Configuration Bytes - Bootloader Start
CAN Microcontrollers
Description
This document describes the UART bootloader functionalities as well as the serial protocol to efficiently perform operations on the on-chip memory. Additional information on the T89C51CC02 product can be found in the T89C51CC02 datasheet and the T89C51CC02 errata sheet available on the Atmel web site, www.atmel.com. The bootloader software Package (source code and binary) currently used for production is available from the Atmel web site.
T89C51CC02 UART Bootloader
Bootloader Revision Revisions 1.2.0
Purpose of Modifications First release
Date 03/12/2002
Rev. 4223B-CAN-12/03
1
Functional Description
In-System Programming Capability
The T89C51CC02 Bootloader facilitates In-System Programming and In-Application Programming. In-System Programming (ISP) allows the user to program or reprogram a microcontroller's on-chip Flash memory without removing it from the system and without the need of a pre-programmed application. The UART bootloader can manage a communication with a host through the serial network. It can also access and perform requested operations on the on-chip Flash memory.
In-Application Programming or Self Programming Capability
In-Application Programming (IAP) allows the reprogramming of a microcontroller's onchip Flash memory without removing it from the system and while the embedded application is running. The UART bootloader contains some Application Programming Interface routines named API routines allowing IAP by using the user's firmware.
Block Diagram
This section describes the different parts of the bootloader. The figure below shows the on-chip bootloader and IAP processes. Figure 1. Bootloader Process Description
On chip User Application
External host via the UART Protocol Communication
ISP Communication Management
IAP User Call Management
Flash Memory Management
Flash Memory
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ISP Communication Management
The purpose of this process is to manage the communication and its protocol between the on-chip bootloader and an external device (host). The on-chip bootloader implements a Serial protocol (see Section "Protocol", page 9). This process translates serial communication frames (UART) into Flash memory accesses (read, write, erase...). Several Application Program Interface (API) calls are available to the application program to selectively erase and program Flash pages. All calls are made through a common interface (API calls) included in the bootloader. The purpose of this process is to translate the application request into internal Flash Memory operations. This process manages low level accesses to the Flash memory (performs read and write accesses).
User Call Management
Flash Memory Management
Bootloader Configuration
Configuration and Manufacturer Information The table below lists Configuration and Manufacturer byte information used by the bootloader. This information can be accessed through a set of API or ISP commands.
Mnemonic BSB SBV P1_CF P3_CF P4_CF SSB EB Manufacturer Id1: Family code Id2: Product Name Id3: Product Revision Description Boot Status Byte Software Boot Vector Port 1 Configuration Port 3 Configuration Port 4 Configuration Software Security Byte Extra Byte Default Value FFh FCh FEh FFh FFh FFh FFh 58h D7h BBh FFh
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Mapping and Default Value of Hardware Security Byte
The 4 Most Significant Byte (MSB) of the Hardware Byte can be read/written by software (this area is called Fuse bits). The 4 (Least Significant Byte) LSB can only be read by software and written by hardware in parallel mode (with parallel programmer devices).
Bit Position 7 6 5 4 3 2 1 0 Mnemonic X2B BLJB reserved reserved reserved LB2 LB1 LB0 Default Value U P U U U P U U To lock the chip (see data sheet) Description To start in x1 mode To map the boot area in code area between F800hFFFFh
Note:
U: Unprogram = 1 P: Program = 0
Security
The bootloader has Software Security Byte (SSB) to protect itself from user access or ISP access. The Software Security Byte (SSB) protects from ISP accesses. The command "Program Software Security Bit" can only write a higher priority level. There are three levels of security: * level 0: NO_SECURITY (FFh) This is the default level. From level 0, one can write level 1 or level 2. level 1: WRITE_SECURITY (FEh) In this level it is impossible to write in the Flash memory, BSB and SBV. The Bootloader returns an error message. From level 1, one can write only level 2. level 2: RD_WR_SECURITY (FCh) Level 2 forbids all read and write accesses to/from the Flash memory. The Bootloader returns an error message.
Level 0 Flash/EEPROM Fuse bit BSB & SBV & EB SSB Manufacturer info Bootloader info Erase block Full chip erase Blank Check Any access allowed Any access allowed Any access allowed Any access allowed Read only access allowed Read only access allowed Allowed Allowed Allowed Level 1 Read only access allowed Read only access allowed Read only access allowed Write level2 allowed Read only access allowed Read only access allowed Not allowed Allowed Allowed Level 2 All access not allowed All access not allowed All access not allowed Read only access allowed Read only access allowed Read only access allowed Not allowed Allowed Allowed
*
*
Only a full chip erase command can reset the software security bits.
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Software Boot Vector
The Software Boot Vector (SBV) forces the execution of a user bootloader starting at address [SBV]00h in the application area (FM0). The way to start this user bootloader is described in the section "Boot Process". Figure 2. Software Boot Vector
UART Bootloader
User Bootloader Application [SBV]00h
FM1
FM0
FLIP Software Program
FLIP is a PC software program running under Windows(R) 9x/2K/XP Windows NT (R) and LINUX(R) that supports all Atmel Flash microcontroller and CAN protocol communication media. This software program is available free of charge from the Atmel web site.
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In-System Programming
The ISP allows the user to program or reprogram a microcontroller's on-chip Flash memory through the serial line without removing it from the system and without the need of a pre-programmed application. This section describes how to start the UART bootloader and all higher level protocol over the serial line.
Boot Process
The bootloader can be activated in two ways: * * Hardware condition Regular boot process
Hardware Condition
The Hardware Condition forces the bootloader execution from reset. The default factory Hardware Condition is assigned to port P1. * P1 must be equal to FEh In order to offer the best flexibility, the user can define its own Hardware Condition on one of this following Port: * * * Port1 Port3 Port4 (only bit0 and bit1)
The Hardware Condition configuration are stored in three bytes called P1_CF, P3_CF, P4_CF. These bytes can be modified by the user through a set of API or through an ISP command. There is a priority between P1_CF, P3_CF and P4_CF (see boot process diagram).
Note: The BLJB must ba at 0 (programmed) to be able to restart the bootloader. If the BLJB is equal to 1 (unprogrammed) only the hardware parallel programmer can change this bit (see T89C51CC02 Datasheet for more detail).
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Regular Boot Process
RESET Bit ENBOOT in AUXR1 Register is Initialized with BLJB Inverted
Hardware Boot Process
ENBOOT = 0 PC = 0000h
Yes
BLJB = 1 ENBOOT = 1 PC = F800h
No
No
P1_CF = FFh
Yes
No
P1_CF = P1 Yes
No
P3_CF = FFh
Yes
Software Boot Process
No
P3_CF = P3
No
P4_CF = FFh
Yes
Yes No P4_CF = P4
Yes
BSB = 0
Yes
No
SBV < 3Fh Yes
No
Start Application
Start User Bootloader
Start Bootloader
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Physical Layer
The UART used to transmit information has the following configuration: * * * * * Character: 8-bit data Parity: none Stop: 2 bit Flow control: none Baud rate: autobaud is performed by the bootloader to compute the baud rate chosen by the host.
Frame Description
The Serial Protocol is based on the Intel Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below. Table 1. Intel Hex Type Frame
Record Mark `:' Record length Load Offset Record Type Data or Info Checksum
1 byte
1 byte
2 bytes
1 bytes
n byte
1 byte
* *
Record Mark: - - Record Mark is the start of frame. This field must contain ':'. Record length specifies the number of Bytes of information or data which follows the Record Type field of the record. Load Offset specifies the 16-bit starting load offset of the data Bytes, therefore this field is used only for Data Program Record. Record Type specifies the command type. This field is used to interpret the remaining information within the frame. Data/Info is a variable length field. It consists of zero or more Bytes encoded as pairs of hexadecimal digits. The meaning of data depends on the Record Type. The two's complement of the 8-bit Bytes that result from converting each pair of ASCII hexadecimal digits to one Byte of binary, and including the Record Length field to and including the last Byte of the Data/Info field. Therefore, the sum of all the ASCII pairs in a record after converting to binary, from the Record Length field to and including the Checksum field, is zero. Record length:
*
Load Offset: - -
*
Record Type: -
*
Data/Info: -
*
Checksum: -
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Protocol
Overview An initialization step must be performed after each Reset. After microcontroller reset, t h e b o o tl o a d e r w a it s f o r a n a u t o b a u d s e q u e n c e ( s e e S e c t io n " A u t o b a u d Performances"). When the communication is initialized the protocol depends on the record type issued by the host. Communication Initialization The host initiates the communication by sending a 'U' character to help the bootloader to compute the baudrate (autobaud). Figure 3. Initialization Host Init Communication "U" Bootloader
Performs Autobaud Sends Back `U' Character
If (not received "U") Else Communication Opened
"U"
Autobaud Performances
The bootloader supports a wide range of baud rates. It is also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. Table 2 shows the autobaud capabilities. Table 2. Autobaud Performances
Frequency (MHz) Baudrate (kHz) 1.8432 2 2.4576 3 3.6864 4 5 6 7.3728
2400 4800 9600 19200 38400 57600 115200
Frequency (MHz) Baudrate (kHz)
OK OK OK OK -
OK -
OK OK OK OK OK -
OK OK OK OK
OK OK OK OK OK
OK OK OK -
OK OK OK OK -
OK OK OK OK OK -
OK OK OK OK OK OK OK
-
OK -
8
10
11.0592
12
14.746
16
20
24
26.6
2400 4800 9600 19200
OK OK OK OK
OK OK OK OK
OK OK OK OK
OK OK OK OK
OK OK OK OK
OK OK OK OK
OK OK OK OK
OK OK OK OK
OK OK OK OK
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Frequency (MHz) Baudrate (kHz) 8 10 11.0592 12 14.746 16 20 24 26.6
38400 57600 115200
-
-
OK OK OK
OK -
OK OK OK
OK OK -
OK OK -
OK OK -
OK OK -
Command Data Stream Protocol All commands are sent using the same flow. Each frame sent by the host is echoed by the bootloader. Figure 4. Command Flow Host Sends first character of the Frame ":" ":" Bootloader If (not received ":") Else Sends echo and start reception
Sends frame (made of 2 ASCII characters per Byte) Echo analysis
Gets frame, and sends back echo for each received Byte
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Programming the Flash or EEPROM Data
The flow described below shows how to program data in the Flash memory or in the EEPROM data memory. The bootloader programs on a page of 128 bytes basis when it is possible. The host must take care that: * The data to program transmitted within a frame are in the same page.
Requests from Host
Command Name Record type Load Offset Record length Data[0] ... Data[127]
Program Flash Program EEPROM Data
00h 07h
start address start address
nb of Data nb of Data
x x
... ...
x x
Answers from Bootloader
The boot loader answers with: * * * `.' & `CR' & 'LF' when the data are programmed `X' & `CR' & `LF' if the checksum is wrong `P' & `CR' & `LF' if the Security is set
Flow Description Host
Send Write Command
Bootloader Write Command
Wait Write Command
OR Wait Checksum Error COMMAND ABORTED
Checksum Error
'X' & CR & LF
Send Checksum error
NO_SECURITY
OR Wait Security Error COMMAND ABORTED
'P' & CR & LF
Send Security error
Wait Programming
Wait COMMAND_OK COMMAND FINISHED
'.' & CR & LF
Send COMMAND_OK
Example Programming Data (write 55h at address 0010h in the Flash)
HOST BOOTLOADER : 01 0010 00 55 9A : 01 0010 00 55 9A . CR LF
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Read the Flash or EEPROM Data
The flow described below allows the user to read data in the Flash memory or in the EEPROM data memory. A blank check command is possible with this flow. The device splits into blocks of 16 bytes the data to transfer to the Host if the number of data to display is greater than 16 data bytes.
Requests from Host
Command Name Record Type Record Load Offset Length Data[0] Data[1] Data[2] Data[3] Data[4]
Read Flash Blank check on Flash Read EEPROM Data 04h x 05h start address end Address
00h 01h 02h
Note:
The field "Load offset" is not used.
Answers from Bootloader
The boot loader answers to a read Flash or EEPROM Data memory command: * * * * * * * `Address = data ` & `CR' & 'LF' up to 16 data by line. `X' & `CR' & `LF' if the checksum is wrong `L' & `CR' & `LF' if the Security is set `.' & `CR' & 'LF' when the blank check is ok `First Address wrong' `CR' & `LF' when the blank check is fail `X' & `CR' & `LF' if the checksum is wrong `P' & `CR' & `LF' if the Security is set
The bootloader answers to blank check command:
Flow Description: Blank Check Command Host
Send Blank Check Command
Bootloader Blank Check Command
Wait Blank Check Command
OR Wait Checksum Error COMMAND ABORTED
Checksum Error
'X' & CR & LF
Send Checksum error
Flash Blank
OR
Wait COMMAND_OK COMMAND FINISHED
'.' & CR & LF
Send COMMAND_OK
Wait Address Not Erased COMMAND FINISHED
Address & CR & LF
Send First Address Not Erased
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Example Blank Check ok
HOST BOOTLOADER : 05 0000 04 0000 7FFF 01 78 : 05 0000 04 0000 7FFF 01 78 . CR LF
Blank Check ko at address xxxx
HOST BOOTLOADER : 05 0000 04 0000 7FFF 01 78 : 05 0000 04 0000 7FFF 01 78 xxxx CR LF
Blank Check with checksum error
HOST BOOTLOADER : 05 0000 04 0000 7FFF 01 70 : 05 0000 04 0000 7FFF 01 70 X CR LF CR LF
Flow Description: Read Command Host
Send Display Command
Bootloader Display Command
Wait Display Command
OR Wait Checksum Error COMMAND ABORTED
Checksum error
'X' & CR & LF
Send Checksum Error
RD_WR_SECURITY
OR Wait Security Error COMMAND ABORTED
'L' & CR & LF
Send Security Error
Read Data
All data read
Complete Frame
Wait Display Data
"Address = " "Reading value" CR & LF
Send Display Data
All data read
All data read
COMMAND FINISHED
COMMAND FINISHED
Note:
The maximum size of block is 400h. To read more than 400h Bytes, the Host must send a new command.
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Example Display data from address 0000h to 0020h
HOST BOOTLOADER BOOTLOADER BOOTLOADER BOOTLOADER : 05 0000 04 0000 0020 00 D7 : 05 0000 04 0000 0020 00 D7 0000=-----data------ CR LF 0010=-----data------ CR LF 0020=data CR LF (16 data) (16 data) (1 data)
Program Configuration Information
The flow described below allows the user to program Configuration Information regarding the bootloader functionality. The Boot Process Configuration: - - - - - - BSB SBV P1_CF, P3_CF, P4_CF Fuse bits (BLJB and X2 bits) (see Section "Mapping and Default Value of Hardware Security Byte") SSB EB
Requests from Host
Command Name Record Type Load Offset Record Length Data[0] Data[1] Data[2]
Erase SBV & BSB Program SSB level1
02h 02h
04h 05h
00h 00h 01h 00h 01h
-
Program SSB level2 Program BSB Program SBV Program P1_CF Program P3_CF Program P4_CF Program EB Program bit BLJB 03h Program bit X2 0Ah 03h x 03h 06h
02h value 03h 04h 06h 04h bit value 08h
Note:
1. The field "Load Offset" is not used 2. To program the BLJB and X2 bit the "bit value" is 00h or 01h.
Answers from Bootloader
The bootloader answers with: * * * `.' & `CR' & 'LF' when the value is programmed `X' & `CR' & `LF' if the checksum is wrong `P' & `CR' & `LF' if the Security is set
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Flow Description Host
Send Write Command
Bootloader Write Command
Wait Write Command
OR Wait Checksum Error COMMAND ABORTED
Checksum Error
'X' & CR & LF
Send Checksum Error
NO_SECURITY
OR Wait Security Error COMMAND ABORTED
'P' & CR & LF
Send Security Error
Wait Programming
Wait COMMAND_OK COMMAND FINISHED
'.' & CR & LF
Send COMMAND_OK
Example Programming Atmel function (write SSB to level 2)
HOST BOOTLOADER : 02 0000 03 05 01 F5 : 02 0000 03 05 01 F5. CR LF
Writing Frame (write BSB to 55h)
HOST BOOTLOADER : 03 0000 03 06 00 55 9F : 03 0000 03 06 00 55 9F . CR LF
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Read Configuration Information or Manufacturer Information Requests from Host
The flow described below allows the user to read the configuration or manufacturer information.
Command Name
Record Type
Load Offset
Record Length Data[0] Data[1]
Read Manufacturer Code Read Family Code 00h Read Product Name Read Product Revision Read SSB Read BSB Read SBV Read P1_CF Read P3_CF Read P4_CF Read EB Read HSB (Fuse bit) Read Device ID1 0Eh Read Device ID2 Read Bootloader version 0Fh 0Bh 05h x 02h 07h
00h 01h 02h 03h 00h 01h 02h 03h 04h 05h 06h 00h 00h 01h 00h
Note:
The field "Load Offset" is not used
Answers from Bootloader
The bootloader answers with: * * * `value' & `.' & `CR' & 'LF' when the value is programmed `X' & `CR' & `LF' if the checksum is wrong `P' & `CR' & `LF' if the Security is set
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Flow Description Host
Send Read Command
Bootloader Read Command
Wait Read Command
OR Wait Checksum Error COMMAND ABORTED
Checksum error
'X' & CR & LF
Send Checksum error
RD_WR_SECURITY
OR Wait Security Error COMMAND ABORTED
'L' & CR & LF
Send Security error
Read Value
Wait Value of Data COMMAND FINISHED
'value' & '.' & CR & LF
Send Data Read
Example Read function (read SBV)
HOST BOOTLOADER : 02 0000 05 07 02 F0 : 02 0000 05 07 02 F0 Value . CR LF
Atmel Read function (read Bootloader version)
HOST BOOTLOADER : 02 0000 01 02 00 FB : 02 0000 01 02 00 FB Value . CR LF
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Erase the Flash
The flow described below allows the user to erase the Flash memory. Two modes of Flash erasing are possible: * * Full Chip erase Block erase
The Full Chip erase command erases the whole Flash (16K bytes) and sets some Configuration Bytes at their default values: * * * BSB = FFh SBV = FCh SSB = FFh (NO_SECURITY)
Take care that the full chip erase execution takes few seconds (128 pages)
The full chip erase is always executed whatever the Software Security Byte value is.
Note:
The Block erase command erases only a part of the Flash. Three Blocks are defined in the T89C51CC02: * * Requests from Host
Command Name Record Type Load Offset Record Length Data[0] Data[1]
block0 (From 0000h to 1FFFh) block1 (From 2000h to 3FFFh)
Erase block0 (0k to 8k) 02h Erase block1 (8k to 16k) Full chip erase 03h x 01h 07h 01h
00h 20h -
Answers from Bootloader
As the Program Configuration Information flows, the erase block command has three possible answers: * * * `.' & `CR' & 'LF' when the data are programmed `X' & `CR' & `LF' if the checksum is wrong `P' & `CR' & `LF' if the Security is set
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Flow Description Host
Send Erase Command
Bootloader Erase Command
Wait Erase Command
OR Wait Checksum Error COMMAND ABORTED
Checksum Error
'X' & CR & LF
Send Checksum Error
NO_SECURITY
OR Wait Security Error COMMAND ABORTED
'P' & CR & LF
Send Security Error
Wait Erasing
Wait COMMAND_OK COMMAND FINISHED
'.' & CR & LF
Send COMMAND_OK
Example Full Chip Erase
HOST BOOTLOADER : 01 0000 03 07 F5 : 01 0000 03 07 F5 . CR LF
Erase Block1(8k to 16k)
HOST BOOTLOADER : 02 0000 03 01 20 DA : 02 0000 03 01 20 DA . CR LF
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Start the Application
The flow described below allows to start the application directly from the bootloader upon a specific command reception. Two options are possible: * Start the application with a reset pulse generation (using watchdog). When the device receives this command the watchdog is enabled and the bootloader enters a waiting loop until the watchdog resets the device. Take care that if an external reset chip is used the reset pulse in output may be wrong and in this case the reset sequence is not correctly executed. Start the application without reset A jump at the address 0000h is used to start the application without reset.
*
Requests from Host
Command Name Record type Load Offset Record Length Data[0] Data[1] Data[2] Data[3]
Start application with a reset pulse generation 03h Start application with a jump at "address" x
02h 03h 04h
00h 01h
Address
-
Answer from Bootloader Example
No answer is returned by the device.
Start Application with reset pulse
HOST BOOTLOADER : 02 0000 03 03 00 F8 : 02 0000 03 03 00 F8
Start Application without reset at address 0000h
HOST BOOTLOADER : 04 0000 03 03 01 00 00 F5 : 04 0000 03 03 01 00 00 F5
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In-Application Programming/Selfprogramming
The IAP allows to reprogram a microcontroller's on-chip Flash memory without removing it from the system and while the embedded application is running. The user application can call some Application Programming Interface (API) routines allowing IAP. These API are executed by the bootloader. To call the corresponding API, the user must use a set of Flash_api routines which can be linked with the application. Example of Flash_api routines are available on the Atmel web site on the software application note: C Flash Drivers for the T89C51CC02UA The Flash_api routines on the package work only with the UART bootloader. The Flash_api routines are listed in APPENDIX-2.
API Call
Process The application selects an API by setting R1, ACC, DPTR0 and DPTR1 registers. All calls are made through a common interface "USER_CALL" at the address FFF0h. The jump at the USER_CALL must be done by LCALL instruction to be able to comeback in the application. Before jump at the USER_CALL, the bit ENBOOT in AUXR1 register must be set. Constraints The interrupts are not disabled by the bootloader. Interrupts must be disabled by user prior to jump to the USER_CALL, then re-enabled when returning. Interrupts must also be disabled before accessing EEPROM Data then re-enabled after. The user must take care of hardware watchdog before launching a Flash operation. For more information regarding the Flash writing time see the T89C51CC02 data sheet.
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API Commands
Several types of APIs are available: * * * * * Read/Program Flash and EEPROM Data memory Read Configuration and Manufacturer Information Program Configuration Information Erase Flash Start bootloader
Read/Program Flash and EEPROM Data Memory
All routines to access EEPROM Data are managed directly from the application without using bootloader resources. To read the Flash memory the bootloader is not involved. For more details on these routines see the T89C51CC02 Data sheet sections "Program/Code Memory" and "EEPROM Data Memory" Two routines are available to program the Flash: - - * __api_wr_code_byte __api_wr_code_page
The application program load the column latches of the Flash then call the __api_wr_code_byte or __api_wr_code_page see data sheet in section "Program/Code Memory". Parameter settings
API_name R1 DPTR0 DPTR1 Acc
*
__api_wr_code_byte
02h
Address in Flash memory to write Address of the first Byte to program in the Flash memory
-
Value to write
__api_wr_code_page
09h
Address in XRAM of the first data to program
Number of Byte to program
*
Instruction: LCALL FFF0h.
No special resources are used by the bootloader during this operation
Note:
Read Configuration and Manufacturer Information
*
Parameter settings
API_name R1 DPTR0 DPTR1 Acc
__api_rd_HSB __api_rd_BSB __api_rd_SBV __api_rd_SSB __api_rd_EB __api_rd_manufacturer __api_rd_device_id1
0Bh 07h 07h 07h 07h 00h 00h
0000h 0001h 0002h 0000h 0006h 0000h 0001h
x x x x x x x
return HSB return BSB return SBV return SSB return EB return manufacturer id return id1
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API_name
R1
DPTR0
DPTR1
Acc
__api_rd_device_id2 __api_rd_device_id3 __api_rd_bootloader_version
00h 00h 0Fh
0002h 0003h 0000h
x x x
return id2 return id3 return value
* *
Instruction: LCALL FFF0h. At the complete API execution by the bootloader, the value to read is in the api_value variable.
No special resources are used by the bootloader during this operation
Note:
Program Configuration Information
*
Parameter settings
R1 DPTR0 DPTR1 Acc
API Name
__api_set_X2 __api_clr_X2 __api_set_BLJB __api_clr_BLJB __api_wr_BSB __api_wr_SBV __api_wr_EB __api_wr_SSB_LEVEL0 __api_wr_SSB_LEVEL1 __api_wr_SSB_LEVEL2
0Ah 0Ah 0Ah 0Ah 06h 06h 06h 05h 05h 05h
0008h 0008h 0004h 0004h 0000h 0001h 0006h FFh FEh FCh
x x x x x x x x x x
00h 01h 00h 01h value to write value to write value to write x x x
*
Instruction: LCALL FFF0h.
1. See in the T89C51CC02 data sheet the time that a write operation takes. 2. No special resources are used by the bootloader during these operations
Note:
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Erase Flash
The T89C51CC02 flash memory is divided in several blocks: Block 0: from address 0000h to 1FFFh Block 1: from address 2000h to 3FFFh These two blocks contain 64 pages. * Parameter settings
R1 Dptr0 Dptr1 Acc
API Name
__api_erase_block0 01h __api_erase_block1
0000h 2000h
x x
x x
*
Instruction: LCALL FFF0h.
1. See the T89C51CC02 data sheet for the time that a write operation takes and this time must multiply by the number of pages. 2. No special resources are used by the bootloader during these operations
Note:
Start Bootloader
This routine allows to start at the beginning of the bootloader as after a reset. After calling this routine the regular boot process is performed and the communication must be opened before any action. * * * No special parameter setting Set bit ENBOOT in AUXR1 register instruction: LJUMP or LCALL at address F800h
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Appendix-A
Table 3. Summary of frames from Host
Command Record Type Record Length Offset Data[0] Data[1] Data[2] Data[3] Data[4]
Program Nb Data Byte in Flash. Erase block0 (0000h-1FFFh)
00h
nb of data (up to 80h) 02h
start address x
x
x 00h
x address value value value value value value bit value bit value
x -
x -
01h 20h
Erase block1 (2000h-3FFFh) Start application with a reset pulse generation Start application with a jump at "address" Erase SBV & BSB Program SSB level 1 Program SSB level 2 Program BSB Program SBV Program P1_CF 03h Program P3_CF Program P4_CF Program EB Full Chip Erase Program bit BLJB 03h Program bit X2 Read Flash Blank Check Read EEPROM Data 04h 05h x x 01h x x x x x 0Ah 07h 03h 02h 02h 04h x 03h x x x 05h x x x x 06h 04h
00h 01h 00h 00h 01h 00h 01h 02h 03h 04h 06h 04h 08h
-
00h
Start Address
End Address
01h 02h
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Table 3. Summary of frames from Host (Continued)
Command Record Type Record Length Offset Data[0] Data[1] Data[2] Data[3] Data[4]
Read Manufacturer Code Read Family Code 00h Read Product Name Read Product Revision Read SSB Read BSB Read SBV Read P1_CF Read P3_CF Read P4_CF Read EB Read Hardware Byte Read Device Boot ID1 0Eh Read Device Boot ID2 Read Bootloader Version Program Nb Data byte in EEPROM 00h nb of data (up to 80h) start address 0Fh x 0Bh 05h 02h x 07h
00h 01h 02h 03h 00h 01h 02h 03h 04h 05h 06h 00h 00h 01h 00h x
x
x
x
26
4223B-CAN-12/03
Appendix-B
Table 4. API Summary
Function Name Bootloader Execution R1 DPTR0 DPTR1 Acc
__api_rd_code_byte
no Address in Flash memory to write Address of the first Byte to program in the Flash memory 0000h 2000h 0000h 0008h 0008h 0004h 0004h 0001h 0000h 0002h 0001h 0001h 0000h 00FFh 00FEh 00FCh 0006h 0006h 0000h 0001h 0002h 0003h 0000h
__api_wr_code_byte
yes
02h
-
Value to write
__api_wr_code_page
yes
09h
Address in XRAM of the first data to program x x x x x x x x x x x x x x x x x x x x x x x
Number of Byte to program
__api_erase_block0 __api_erase_block1 __api_rd_HSB __api_set_X2 __api_clr_X2 __api_set_BLJB __api_clr_BLJB __api_rd_BSB __api_wr_BSB __api_rd_SBV __api_wr_SBV __api_erase_SBV __api_rd_SSB __api_wr_SSB_level0 __api_wr_SSB_level1 __api_wr_SSB_level2 __api_rd_EB __api_wr_EB __api_rd_manufacturer __api_rd_device_id1 __api_rd_device_id2 __api_rd_device_id3 __api_rd_bootloader_version __api_eeprom_busy __api_rd_eeprom_byte __api_wr_eeprom_byte __api_start_bootloader
yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes no no no no
01h 01h 0Bh 0Ah 0Ah 0Ah 0Ah 07h 06h 07h 06h 06h 07h 05h 05h 05h 07h 06h 00h 00h 00h 00h 0Fh
x x return value 00h 01h 00h 01h return value value return value value FCh return value x x x return value value return value return value return value return value return value
27
4223B-CAN-12/03
Table of Contents
Features ................................................................................................. 1 Description ............................................................................................ 1 Functional Description ......................................................................... 2
In-System Programming Capability ......................................................................2 In-Application Programming or Self Programming Capability ...............................2 Block Diagram ......................................................................................................2 Bootloader Configuration ......................................................................................3 Security .................................................................................................................4 Software Boot Vector ............................................................................................5 FLIP Software Program ........................................................................................5
In-System Programming ...................................................................... 6
Boot Process ........................................................................................................6 Physical Layer ......................................................................................................8 Protocol .................................................................................................................9
In-Application Programming/Self-programming ............................. 21
API Call ...............................................................................................................21 API Commands ................................................................................................... 22
Appendix-A .......................................................................................... 25 Appendix-B .......................................................................................... 27
i
4208A-CAN-11/02
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